--A Recursive Structure Power Aware Block based Imprecise Multiplier--
-- Eric Zhang & Xinfei Guo Copyright --

Design Delivery Content

1. Schematic Files
	-1.1 Conventional Schematic Files
		The directory includes all the schematics of the conventional Wallace Tree/Array Multiplier. The top level schematic for 8-bit and 32-bit Wallace Tree are 8bWallaceTree and 32bWallaceTree seperately.
	-1.2 PABAIM
		This directory includes all of our design for PABAIM. The top level schematic for 8-bit and 32-bit PABAIM are in 8-bit PABAIM and 32-bit PABAIM, seperately.

2. Simulation Files
	-Simulation Files include all the netlist and ocean script for Mente Carlo Simulation.
	-.sp are netlist files
	-.py are random input vector generating files 
	-hsim_setup and vectorgen.pl are setup files for hsim
	* To run simulation:
		1. . hsim_setup
		2. perl vectorgen.pl [stimulus file]
		3. hsim -i [testbench.sp] -o [outputfile]
3. Algorithm
   High level language implementation of the algorithm design including C, JAVA, and Python


A tree structure of the directories is shown below:

Algorithm
  C
  JAVA
    IHW
        BitArray
  Python
Schematic Files
  Conventional Design
    10bitRCA
      schematic
      symbol
    10bit_Prefix_Adder
      schematic
      symbol
    11bitAdder
      schematic
    13bitAdder
      schematic
      symbol
    16bitMirrrorAdder
      schematic
      symbol
    1bitFA_RemoveInverter
      schematic
      symbol
    1bitMirrrorAdder
      schematic
      symbol
    2#2dinput#2dMUX
      schematic
      symbol
    2#2dinputANDGate
      schematic
      symbol
    2#2dinputORGate
      schematic
      symbol
    2bitadder
      schematic
      symbol
    2bitMultiplier
      schematic
      symbol
    2bitMultiplier_Updated
      schematic
      symbol
    2inputXOR
      schematic
      symbol
    2X1MUX_Updated
      schematic
      symbol
    2X1XOR_Updated
      schematic
      symbol
    3#2dinput#2dMUX
      schematic
      symbol
    3#2dinputAND
      schematic
      symbol
    3#2dinputANDGate
      schematic
      symbol
    3#2dinputORGate
      schematic
      symbol
    32bWallaceTree
      schematic
    4#2dinputANDGate
      schematic
      symbol
    4#2dinputORGate
      schematic
      symbol
    4bitFA_Inv
      schematic
      symbol
    4bitMirrrorAdder
      schematic
      symbol
    4BIT_ADDER
      schematic
      symbol
    4inputMUX
      schematic
      symbol
    5#2dinputAND
      schematic
      symbol
    5#2dinputORGate
      schematic
      symbol
    57bRCA
      schematic
      symbol
    5bitAdder_Inv
      schematic
      symbol
    5bitMirrrorAdder
      schematic
      symbol
    6#2dinputORGate
      schematic
      symbol
    6inputMUX
      schematic
      symbol
    8bPABAIM_Tree
      schematic
    8bPABAIM_Tree_ZeroDetec
      schematic
    8bPABAIM_Updated
      schematic
    8bPABAIM_WithoutZeroDetection
      schematic
    8bWallaceTree
      schematic
    8TFullAdder
      schematic
    Blcakbox
      schematic
      symbol
    BlockMultiplier_Control_WithoutZeroDetection
      schematic
      symbol
    BlockMultiplier_Control_WithoutZeroDetection_Tree
      schematic
      symbol
    BlockMultiplier_ZeroDetector
      schematic
      symbol
    BlockMultiplier_ZeroDetector_Control
      schematic
      symbol
    BlockMultiplier_ZeroDetector_Control_Tree
      schematic
      symbol
    Casetest1
      schematic
    Casetest2
      schematic
    Comparater
      schematic
      symbol
    Comparater_Updated
      schematic
      symbol
    Controller
      schematic
      symbol
    Controller_Updated
      schematic
      symbol
    DiagonalAddtion
      schematic
      symbol
    FinalSchemetic
      schematic
      symbol
    FooterNMOS
      schematic
      symbol
    FooterNMOS_4bit
      schematic
      symbol
    FooterNMOS_5bit
      schematic
      symbol
    FooterNMOS_Row1
      schematic
      symbol
    FooterNMOS_Row1_NoZero
      schematic
      symbol
    FooterNMOS_Row2
      schematic
      symbol
    FooterNMOS_Row2_NoZero
      schematic
      symbol
    FooterNMOS_Row3
      schematic
      symbol
    FooterNMOS_Row3_NoZero
      schematic
      symbol
    FooterNMOS_Row4
      schematic
      symbol
    FooterNMOS_Row4_NoZero
      schematic
      symbol
    Graybox
      schematic
      symbol
    Inverter
      schematic
      symbol
    MisalignedParallelAddition
      constraint
      schematic
      symbol
    MUX_Array_A0B0
      schematic
      symbol
    MUX_Array_A0B3
      schematic
      symbol
    MUX_Array_A1B0
      schematic
      symbol
    MUX_Array_A1B2
      schematic
      symbol
    MUX_Array_A2B0
      schematic
      symbol
    MUX_Array_A2B1
      schematic
      symbol
    NOR
      schematic
      symbol
    OR_Updated
      schematic
      symbol
    Powergating
      schematic
      symbol
    Powergating_test
      schematic
    Powergating_Test2
      schematic
    PreprocessingBlock
      schematic
      symbol
    tb_1bitMirrrorAdder
      schematic
    TB_Controller
      schematic
    TB_FinalSchemetic
      schematic
    tb_Multiplier
      schematic
    tb_NOR
      schematic
    tb_OR
      schematic
    tb_Updated_Toplevel
      schematic
    TB_Version1
      schematic
    tb_XOR
      schematic
    Updated_TopLevelSchematic
      schematic
      symbol
    Version1
      schematic
      symbol
    ZeroDetector
      schematic
      symbol
    ZeroDetector_Row
        schematic
        symbol
  PABAIM
      32-bit PABAIM
        2bOR
          schematic
        2T0Dectector
          schematic
          symbol
        4b2T0Dectector
          schematic
          symbol
        4bitArrayMultiplier
          schematic
          symbol
        4bitMultiplierRecursive
          schematic
          symbol
        BLOCK_MULTIPLICATION
          schematic
        BLOCK_MULTIPLICATION_Recursive
          schematic
          symbol
        finalRCA
          schematic
          symbol
        MUX2X1
          schematic
          symbol
        NMOS_FOOTER
          schematic
          symbol
        PABAIM
          schematic
        tb2T0Dectector
          schematic
        tb4b2T0Dectector
          schematic
        TB4bitArrayMultiplier
          schematic
        tb_2T0Dectector
          schematic
        TREE_ACCUMULATION
            schematic
            symbol
      8-bit PABAIM
          10bitRCA
            schematic
            symbol
          11bitRCA
            schematic
            symbol
          2bArrayMultiplier
            schematic
          2bitMultiplier
            schematic
            symbol
          2bitMultiplier_combin
            schematic
          2bitMultiplier_HA
            schematic
          2BIT_BUS
            schematic
            symbol
          3BIT_BUS
            schematic
            symbol
          3BIT_OR
            schematic
            symbol
          4BIT_4TO2CSA
            schematic
            symbol
          4BIT_ADDER
            schematic
            symbol
          4BIT_BUS
            schematic
            symbol
          4BIT_CSA
            schematic
            symbol
          5bitAdder
            schematic
            symbol
          5BIT_Adder
            schematic
            symbol
          8bPABAIM
            adexl
              documents
              results
                data
              states
              test_states
                  8bPABAIM
                      8bPABAIM
                          spectre
                              8bPABAIM%3A8bPABAIM%3A1_active
                              8bPABAIM%3A8bPABAIM%3A1_tb_8bPABAIM_transient128_129X255lowvdd_MonteCarlo.0
                              tb_8bPABAIM_transient128_129X255lowvdd
            schematic
            symbol
          8BPABAIM_NEW
            schematic
          8bPABAIM_Tree
            schematic
          8bPABAIM_updated
            schematic
          8bWallaceTree
            schematic
          AND
            schematic
            symbol
          BlockMultilication
            schematic
            symbol
          BlockMultilicationTree
            schematic
            symbol
          BlockMultilication_xb#3d0
            schematic
          BlockMultilication_xb#3d1
            schematic
          BlockMultilication_xb#3d2
            schematic
          BlockMultilication_xb#3d3
            schematic
          BlockMultilication_xb#3d4
            schematic
          BlockMultilication_xb#3d5
            schematic
          BlockMultilication_xb#3d6
            schematic
          BlockMultiplication_backup
            schematic
          CSA3TO2
            schematic
            symbol
          CSA3TO2_OPTMIZED
            schematic
            symbol
          DiagonalAddtion
            schematic
            symbol
          DiagonalAddtion_OPTIMIZED
            schematic
            symbol
          FinalStageAccumulation
            schematic
            symbol
          FinalStageAccumulation_new
            schematic
          FINAL_ADDITION_NEW
            schematic
            symbol
          inverter
            schematic
            symbol
          levelShifter
            schematic
          MisalignedParallelAddition
            schematic
            symbol
          oceansim
            .cadence
              dfII
                  viva
            result
              psf
            test
          pabaimwz
            schematic
          psf
          TB_8bPABAIM
            schematic
          TransFA
            schematic
            symbol
          TreeAccumulation
            schematic
            symbol
          TreeAccumulation_Opt
              schematic
              symbol
Simulation Files
    ihnl
      cds0
      cds1
      cds2
      cds3
      cds4
      cds5
      cds6
      cds7
      cds8
      cds9
    map
    raw
